Principal STA Engineer: Timing Signoff Leader

Tessolve; San Jose (CA); On-site; USD 170,000 - 240,000; Full time

Job summary

Tessolve is seeking a Principal STA Engineer to join our San Jose team to lead timing analysis and signoff for cutting-edge ASIC/SOC designs. You will drive timing closure across multi‑clock/multi‑voltage architectures and collaborate with RTL, Physical Design, DFT, CTS, and CAD teams to enable successful tape-outs at advanced nodes.

The ideal candidate has 10+ years in STA, deep technical leadership, and strong scripting skills.

Qualifications

• 10+ years of STA and timing signoff experience in ASIC/SOC programs
• Bachelor’s or Master’s degree in Electronics/Electrical Engineering, VLSI, or related field
• Strong setup/hold analysis, CTS interaction, and timing convergence techniques
• Hands-on with PrimeTime, Tempus, StarRC, and related signoff tools
• Experience with 7nm, 5nm or below technology nodes
• Strong scripting skills in Tcl, Python, Perl or Shell
• Excellent leadership, debugging, communication, and stakeholder management skills

Responsibilities

• Lead end-to-end STA and timing signoff for full-chip and subsystem designs
• Drive timing closure across setup, hold, SI, noise, crosstalk, IR-aware timing, MMMC
• Define timing constraints, validate SDCs, ensure robust timing methodology
• Timing closure for low-power designs and optimize power during timing
• Advise design teams on changes to meet timing and reduce power
• Collaborate with RTL, Physical Design, DFT, CTS, and CAD teams
• Mentor engineers and lead technical reviews for timing architecture
• Support ECO implementation and signoff verification for advanced node tape-outs
• Develop automation flows, scripts, and timing dashboards

Skills

STA/timing signoff

Scripting (Tcl/Python/Perl/Shell)

Leadership & stakeholder management

Debugging & problem solving

Education

Bachelor’s or Master’s in Electronics/Electrical Engineering or VLSI

Tools

Synopsys PrimeTime

Synopsys Tempus

StarRC

Job description

Tessolve is seeking a Principal STA Engineer to join our San Jose team to lead timing analysis and signoff for cutting-edge ASIC/SOC designs. You will drive timing closure across multi‑clock/multi‑voltage architectures and collaborate with RTL, Physical Design, DFT, CTS, and CAD teams to enable successful tape-outs at advanced nodes.

The ideal candidate has 10+ years in STA, deep technical leadership, and strong scripting skills.