Senior ASIC STA Engineer — Timing & Full-Chip Mastery

Tensordyne; Sunnyvale (CA); Remote; USD 180,000 - 260,000; Full time

Benefits offered by this job

Comprehensive benefits

Competitive compensation

Flexible spending options

Remote work across NA/Europe

Job summary

Tensordyne, a Sunnyvale-based AI system solutions company, is seeking a senior ASIC STA lead to drive frontend physical design and timing closure across full-chip and block-level workstreams. You will collaborate with a global team, develop scalable STA workflows, and optimize timing with Cadence/Synopsys tools in a fast-paced HPC environment.

Ideal candidates have 10+ years in ASIC design, strong SDC skills for PCIe/SerDes interfaces, and a track record leading backend teams, while enjoying a

Qualifications

• 10+ years in ASIC engineering with VLSI/SoC workflows and EDA tooling.
• Ability to write SDCs for high-speed IP interfaces (PCIe, SerDes).
• Individual contributor tech lead owning full-chip timing closure and signoff.
• Experience leading backend design support with STA timing issues and ECO generation.

Responsibilities

• Lead the ASIC physical design STA efforts across block and full-chip timing closure.
• Develop and optimize frontend physical design workflows and timing exploration.
• Collaborate with ASIC team members across global locations to improve EDA needs.

Skills

ASIC engineering

STA timing analysis

VLSI/SoC design

Technical leadership

GenAI & EDA workflows

SDC scripting

Strong communication

Education

Bachelor’s or Master’s in CS/CE/EE

Tools

Cadence PrimeTime

Synopsys Tempus

Genus

Innovus

Job description

Tensordyne, a Sunnyvale-based AI system solutions company, is seeking a senior ASIC STA lead to drive frontend physical design and timing closure across full-chip and block-level workstreams. You will collaborate with a global team, develop scalable STA workflows, and optimize timing with Cadence/Synopsys tools in a fast-paced HPC environment.

Ideal candidates have 10+ years in ASIC design, strong SDC skills for PCIe/SerDes interfaces, and a track record leading backend teams, while enjoying a