Senior ASIC Timing Engineer — Equity + High-Impact Innovation

Google LLC; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Benefits

Bonus target 15%

Job summary

Google Sunnyvale, CA, USA is seeking a Static Timing Engineer to lead the timing closure for high-performance compute ASICs. You will develop constraints, automate timing flows, and collaborate with architecture, logic design, and DFT teams to meet tight performance and power goals.

You will work on advanced technology nodes, develop methodologies, and evaluate vendors/tools. In-person interviews are typically required as part of the hiring process.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with static timing analysis.
• Experience in Primetime or Tempus Tcl scripting and static timing analysis debug.
• Experience in full chip timing sign-off checklist criteria and overseeing final timing sign-off for ASICs.

Responsibilities

• Work on the physical implementation of ASICs using advanced technology nodes, constraint development and validation, and timing closure.
• Develop static timing methodologies, margins, automation scripts, and write documentation.
• Perform technical evaluations of vendors, tools, methodologies, and provide recommendations.
• Collaborate with architecture, logic design, and DFT teams to understand and implement their requirements.

Skills

Static timing analysis

Primetime/Tempus Tcl

Tcl scripting

Timing sign-off

ASIC timing sign-off

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Master's or PhD in Electrical/Computer Engineering or Computer Science (computer architecture emphasis)

Tools

Perl

Python

Tcl

Bash

Job description

Google Sunnyvale, CA, USA is seeking a Static Timing Engineer to lead the timing closure for high-performance compute ASICs. You will develop constraints, automate timing flows, and collaborate with architecture, logic design, and DFT teams to meet tight performance and power goals.

You will work on advanced technology nodes, develop methodologies, and evaluate vendors/tools. In-person interviews are typically required as part of the hiring process.