Principal STA Engineer

Tessolve; San Jose (CA); On-site; USD 170,000 - 240,000; Full time

Job summary

Tessolve is seeking a Principal STA Engineer to join our San Jose team to lead timing analysis and signoff for cutting-edge ASIC/SOC designs. You will drive timing closure across multi‑clock/multi‑voltage architectures and collaborate with RTL, Physical Design, DFT, CTS, and CAD teams to enable successful tape-outs at advanced nodes.

The ideal candidate has 10+ years in STA, deep technical leadership, and strong scripting skills.

Qualifications

• 10+ years of STA and timing signoff experience in ASIC/SOC programs
• Bachelor’s or Master’s degree in Electronics/Electrical Engineering, VLSI, or related field
• Strong setup/hold analysis, CTS interaction, and timing convergence techniques
• Hands-on with PrimeTime, Tempus, StarRC, and related signoff tools
• Experience with 7nm, 5nm or below technology nodes
• Strong scripting skills in Tcl, Python, Perl or Shell
• Excellent leadership, debugging, communication, and stakeholder management skills

Responsibilities

• Lead end-to-end STA and timing signoff for full-chip and subsystem designs
• Drive timing closure across setup, hold, SI, noise, crosstalk, IR-aware timing, MMMC
• Define timing constraints, validate SDCs, ensure robust timing methodology
• Timing closure for low-power designs and optimize power during timing
• Advise design teams on changes to meet timing and reduce power
• Collaborate with RTL, Physical Design, DFT, CTS, and CAD teams
• Mentor engineers and lead technical reviews for timing architecture
• Support ECO implementation and signoff verification for advanced node tape-outs
• Develop automation flows, scripts, and timing dashboards

Skills

STA/timing signoff

Scripting (Tcl/Python/Perl/Shell)

Leadership & stakeholder management

Debugging & problem solving

Education

Bachelor’s or Master’s in Electronics/Electrical Engineering or VLSI

Tools

Synopsys PrimeTime

Synopsys Tempus

StarRC

Job description

One of our valued customer is looking for Principal STA Engineer at San Jose, CA

Principal STA Engineer

San Jose, CA

Role Overview

We are seeking a highly experienced Principal Engineer – STA to lead timing analysis and signoff activities for advanced ASIC/SOC designs. The role requires deep expertise in static timing analysis methodologies, timing closure strategies, and signoff convergence across complex multi-clock, multi-voltage, and high-performance designs. The ideal candidate will provide technical leadership, drive cross-functional collaboration, and enable successful tape-outs at advanced technology nodes.

Responsibilities

• Lead end-to-end STA and timing signoff activities for full-chip and subsystem-level designs.
• Drive timing closure across setup, hold, SI, noise, crosstalk, IR-aware timing, and MMMC scenarios.
• Define timing constraints, validate SDCs, and ensure robust timing methodology execution.
• Timing closure for very low power designs. Anaylyze the timing closed SOC to reduce both dynamic and static power.
• Advise design team for any design changes which could meet timing requirements and still reduce power.
• Collaborate closely with RTL, Physical Design, DFT, CTS, and CAD teams to achieve timing convergence.
• Analyze and resolve complex timing violations and critical path bottlenecks.
• Support ECO implementation and signoff verification for advanced node tape-outs.
• Develop and improve automation flows, scripts, timing dashboards, and methodology enhancements.
• Mentor engineers and lead technical reviews for timing architecture and signoff readiness.

Requirements

• 10+ years of experience in STA and timing signoff for ASIC/SOC programs.
• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field.
• Strong expertise in setup/hold analysis, timing exceptions, CTS interaction, and timing convergence techniques.
• Hands-on experience with Synopsys PrimeTime, Tempus, StarRC, and related signoff tools.
• Strong understanding of SI, OCV/AOCV/POCV, CDC, low-power timing methodologies, and advanced node effects.
• Experience with advanced technology nodes such as 7nm, 5nm, or below.
• Strong scripting skills in Tcl, Python, Perl, or Shell scripting.
• Excellent technical leadership, debugging, communication, and stakeholder management skills.

Good to Have

• Experience with package-aware timing analysis and chiplet architectures.
• Exposure to AI/ML-driven timing optimization methodologies.