Senior ASIC Timing Engineer - Equity Eligible

NVIDIA; Santa Clara (CA); On-site; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity and benefits

Stock option plan

Job summary

NVIDIA in Santa Clara is seeking an ASIC Timing Engineer to drive timing analysis and closure for GPUs, CPUs, LPUs and SoCs. You will work with RTL, DFX, clocks teams to devise timing strategies and implement ECOs.

We value hands-on STA, timing convergence, and power optimization, with experience in full-chip timing paths and crosstalk analysis. Join a team delivering cutting-edge AI hardware at scale.

Qualifications

• BS or MS in Electrical or Computer Engineering with 5+ years (BS) or 3+ years (MS) in timing and STA.
• Hands-on full-chip/sub-chip STA and timing convergence experience.
• Experience generating and managing timing constraints.
• Knowledge of deep sub-micron processes is beneficial.

Responsibilities

• Drive timing analysis and closure for GPUs, CPUs, LPUs and SoCs at block, cluster and full-chip levels.
• Collaborate with RTL, DFX, Clocks and other teams to devise timing strategies and implement ECOs.
• Improve timing convergence flows in collaboration with methodology teams.

Skills

STA

Timing analysis

Timing closure

Timing constraints

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Job description

NVIDIA in Santa Clara is seeking an ASIC Timing Engineer to drive timing analysis and closure for GPUs, CPUs, LPUs and SoCs. You will work with RTL, DFX, clocks teams to devise timing strategies and implement ECOs.

We value hands-on STA, timing convergence, and power optimization, with experience in full-chip timing paths and crosstalk analysis. Join a team delivering cutting-edge AI hardware at scale.