Senior Static Timing Engineer – ASIC Timing & Automation

Google; Town of Montana (WI); On-site; USD 163,000 - 236,000; Full time

Job summary

Google is seeking a Senior Static Timing Engineer in Sunnyvale, CA, to lead the physical implementation of high-performance ASICs. You will develop constraints, validate timing, and drive timing closure for large compute chips, collaborating with architecture, logic, and DFT teams.

The role requires hands-on STA expertise, scripting in Tcl/Perl/Python, and evaluating tools and vendors to ensure robust sign-off across complex design flows.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with static timing analysis.
• Experience in Primetime or Tempus Tcl scripting and static timing analysis debug.
• Experience in full chip timing sign-off checklist criteria and overseeing final timing sign-off for ASICs.

Responsibilities

• Perform full chip static timing analysis, timing ECO creation for timing convergence, and final timing sign-off for ASIC tape outs.
• Debug and resolve common STA or design rule issues like unconstrained endpoints, maximum transition, minimum period, or minimum pulse width violations.
• Develop timing constraints and verify them for sign-off.
• Utilize Perl, Python, Tcl, or Bash to create static timing flow automation scripts.
• Own and maintain Primetime STA flows.

Skills

Static timing analysis

Tcl scripting

ASIC timing sign-off

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Primetime

Tempus Tcl scripting

Job description

Google is seeking a Senior Static Timing Engineer in Sunnyvale, CA, to lead the physical implementation of high-performance ASICs. You will develop constraints, validate timing, and drive timing closure for large compute chips, collaborating with architecture, logic, and DFT teams.

The role requires hands-on STA expertise, scripting in Tcl/Perl/Python, and evaluating tools and vendors to ensure robust sign-off across complex design flows.