SRAM Design Lead – High-Performance Memory

Micron Technology, Inc.; Boise (ID); Hybrid; USD 153,000 - 267,000; Full time

Job summary

Micron Technology, Inc. in Boise is seeking an experienced SRAM Design Lead to develop high-performance, low-power embedded memory IP and testchip content across advanced technologies.

You will own transistor‑level design, architecture, and validation from concept through signoff, collaborating with layout, CAD, process, and silicon-test teams. The role emphasizes bitcell and peripheral circuit design, timing, power analysis, and PPA optimization, with leadership to mentor engineers and advance

Qualifications

• Hands-on experience with SRAM and register-file circuit design from architecture to signoff.
• Experience with memory-array subsystems including bitcells, decoders, and sense amps.
• Strong skills in transistor-level circuit design and timing/power characterization.
• Experience with post-layout verification and signoff.
• Ability to model and optimize PPA across PVT conditions.

Responsibilities

• Design and optimize custom SRAM and embedded-memory circuits from architecture to release.
• Develop and verify memory-array subsystems including bitcells, precharge, sense amplifiers.
• Evaluate stability, performance, leakage, dynamic power across PVT and aging.
• Lead pre-silicon verification and post-silicon characterization with cross-functional teams.
• Collaborate with layout, CAD, process/foundry, and silicon-test teams.
• Mentor engineers and drive automation for memory development.

Skills

SRAM design

Register-file design

Memory architectures

Bitcell arrays

Read/write datapaths

Sense amplifiers

Address decoding

Control logic

PPA tradeoffs

Low-power design

Education

BS/MS/PhD in Electrical Engineering or related field

Tools

Cadence Virtuoso

HSPICE

Spectre

FineSim

Python

Job description

Micron Technology, Inc. in Boise is seeking an experienced SRAM Design Lead to develop high-performance, low-power embedded memory IP and testchip content across advanced technologies.

You will own transistor‑level design, architecture, and validation from concept through signoff, collaborating with layout, CAD, process, and silicon-test teams. The role emphasizes bitcell and peripheral circuit design, timing, power analysis, and PPA optimization, with leadership to mentor engineers and advance