Senior SRAM Design Lead – Low-Power Memory Architect

Micron

Boise (ID)

On-site

USD 120,000 - 180,000

Full time

4 days ago
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Job summary

Micron Technology is seeking an experienced SRAM Design Engineer to develop high-performance, low-power memory IP and testchip content across advanced technologies. You will contribute from architecture through signoff, collaborating with layout, verification, and product teams to ensure robust memory solutions.

The role involves designing SRAM and embedded-memory circuits, evaluating performance, power, and area, and driving PPA optimization through careful circuit sizing, timing, and

Qualifications

  • BS/MS/PhD in Electrical Engineering or related field.
  • Experience in SRAM and embedded memory architectures.
  • Strong pre-/post-silicon verification and characterization skills.
  • Ability to collaborate across layout, verification, and product teams.

Responsibilities

  • Design and optimize SRAM, register-file, and embedded-memory circuits across architecture through schematic and layout support.
  • Lead pre-silicon verification, silicon bring-up, and memory-model validation.
  • Drive PPA optimization via circuit sizing, timing, and power characterization.
  • Define timing, power, and functional characterization methodologies for memory models and SoC integration.

Skills

SRAM design
Memory IP development
PPA optimization
Circuit verification
Python scripting

Education

BS/MS/PhD in Electrical Engineering or related field

Tools

HSPICE
Spectre
FineSim
SPICE
Python
Tcl
Perl
SKILL

Job description

Micron Technology is seeking an experienced SRAM Design Engineer to develop high-performance, low-power memory IP and testchip content across advanced technologies. You will contribute from architecture through signoff, collaborating with layout, verification, and product teams to ensure robust memory solutions.

The role involves designing SRAM and embedded-memory circuits, evaluating performance, power, and area, and driving PPA optimization through careful circuit sizing, timing, and

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