Staff DRAM Design Engineer — Memory Architect

Micron Technology, Inc; Boise (ID); On-site; USD 120,000 - 170,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision plans

Paid time off

Paid holidays

Relocation assistance

Job summary

Micron Technology, Inc. in Boise, Idaho seeks a Staff DRAM Design Engineer to shape memory architectures and drive circuit innovations from concept through silicon validation.

You will lead DRAM circuit design, analyze trade-offs for power and performance, and collaborate with cross-functional teams to deliver scalable memory solutions. Ideal candidates bring a strong background in analog/digital fundamentals, CMOS timing, and circuit simulation.

Qualifications

• Bachelors degree in Electrical Engineering or related field.
• 2+ years of circuit design experience or 4+ years of product engineering experience.
• Strong understanding of analog and digital circuit fundamentals and debugging.
• Experience with circuit simulation tools and methodologies.
• Knowledge of CMOS behavior, timing, and performance optimization.

Responsibilities

• Lead design and optimization of DRAM circuits including memory array, control logic, datapath, and test logic.
• Perform and analyze circuit simulations using tools such as SPICE and Verilog.
• Evaluate architectural trade-offs impacting power, performance, and die size.
• Integrate layout parasitics into simulations and drive design for manufacturability.
• Define validation strategies including test chip development and silicon bring-up.

Skills

Circuit design

Analog & digital

SPICE/Verilog

CMOS timing

Debugging

Cross-team communication

Education

Bachelors degree in Electrical Engineering

Tools

SPICE

Verilog

DFT/DFM concepts

Circuit simulation tools

Job description

Micron Technology, Inc. in Boise, Idaho seeks a Staff DRAM Design Engineer to shape memory architectures and drive circuit innovations from concept through silicon validation.

You will lead DRAM circuit design, analyze trade-offs for power and performance, and collaborate with cross-functional teams to deliver scalable memory solutions. Ideal candidates bring a strong background in analog/digital fundamentals, CMOS timing, and circuit simulation.