SRAM Design Lead - Low-Power Memory Architect

Micron Technology, Inc.; City of Albany (NY); On-site; USD 153,000 - 267,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Paid time off and holidays

Equity programs

Job summary

Micron Technology, Inc. in the United States is seeking an experienced SRAM Design Engineer to create high-performance, low-power embedded-memory IP and testchip content.

You will contribute across the full memory-development lifecycle, from architecture to post-silicon validation, partnering with layout, CAD, and foundry teams. The role requires hands-on SRAM and register-file design, bitcell stability analysis, and transistor-level sign-off using HSPICE, Spectre, or FineSim.

Qualifications

• BS/MS/PhD in Electrical Engineering, Electronics, VLSI, Microelectronics, or related field.
• Proven SRAM, register-file, ROM/DRAM peripheral design experience.
• Hands-on Cadence Virtuoso and SPICE-class simulators experience.

Responsibilities

• Design and optimize SRAM, register-file, and embedded-memory circuits from architecture to release.
• Develop and verify memory-array subsystems including bitcell arrays and decoders.
• Evaluate bitcell stability, performance, leakage, and area across PVT/mismatch/aging.
• Own transistor-level simulation and sign-off with various tools and corners.
• Drive PPA optimization through sizing, banking, and timing analysis.
• Define characterization methods and generate data for models and SoC integration.

Skills

CMOS transistor-level design

Memory architectures

Pre-silicon verification

Debug and failure analysis

Structured problem solving

Technical communication

Education

BS/MS/PhD in Electrical Engineering or related field

Tools

Cadence Virtuoso

HSPICE

Spectre

FineSim

Parasitic-aware post-layout

Job description

Micron Technology, Inc. in the United States is seeking an experienced SRAM Design Engineer to create high-performance, low-power embedded-memory IP and testchip content.

You will contribute across the full memory-development lifecycle, from architecture to post-silicon validation, partnering with layout, CAD, and foundry teams. The role requires hands-on SRAM and register-file design, bitcell stability analysis, and transistor-level sign-off using HSPICE, Spectre, or FineSim.