SRAM Design Lead: Memory IP & PPA Expert

Micron Technology, Inc.; Boise (ID); On-site; USD 153,000 - 267,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Paid time off

Paid holidays

Family leave

Job summary

Micron Technology, Inc. seeks an experienced SRAM Design Engineer in Boise, Idaho to develop high‑performance, low‑power memory IP and testchip content across advanced technologies.

You will own transistor‑level design, verification, and post‑silicon validation in collaboration with layout, CAD, and silicon-test teams. The role requires hands‑on SRAM and register‑file expertise, PPA tradeoffs, timing and power characterization, and proactive use of automation tools.

Qualifications

• BS/MS/PhD in Electrical Engineering, Electronics, VLSI, Microelectronics, Computer Engineering, or related field.
• Proven experience in SRAM, register-file, ROM, DRAM peripheral, or other custom-memory circuit design.
• Strong knowledge of CMOS transistor-level circuit design, memory architecture, and power analysis.

Responsibilities

• Design and optimize SRAM, register-file, and embedded memory circuits from architecture through schematic and layout support.
• Develop and verify memory-array subsystems including bitcell arrays and sense amplifiers.
• Evaluate stability, performance, leakage, dynamic power, and area across PVT and aging conditions.
• Lead transistor-level simulation and signoff using HSPICE, Spectre, or FineSim with proper corner analyses.
• Drive PPA optimization through sizing, architectural decisions, and retention modes.
• Plan timing, power, and functional characterization for memory models and SoC integration.

Skills

SRAM design

Register-file design

Memory architecture

Timing analysis

Power analysis

CMOS transistor-level design

Python/Tcl/Perl scripting

Education

BS/MS/PhD in Electrical Engineering or related field

Tools

Cadence Virtuoso

HSPICE

Spectre

FineSim

Job description

Micron Technology, Inc. seeks an experienced SRAM Design Engineer in Boise, Idaho to develop high‑performance, low‑power memory IP and testchip content across advanced technologies.

You will own transistor‑level design, verification, and post‑silicon validation in collaboration with layout, CAD, and silicon-test teams. The role requires hands‑on SRAM and register‑file expertise, PPA tradeoffs, timing and power characterization, and proactive use of automation tools.