Senior DRAM Design Engineer, Memory Architect

Micron Technology, Inc.; Boise, Northern (ID, KY); Hybrid; USD 130,000 - 210,000; Full time

Job summary

Micron Technology, Inc. in Boise, Idaho, seeks a Staff DRAM Design Engineer to shape memory architectures and drive circuit innovations from concept to silicon bring-up.

You will lead design and optimization of DRAM circuits, and run SPICE and Verilog simulations. Collaborating with cross-functional teams across the globe, you will guide validation strategies, work on test chips, and contribute to manufacturability with layout parasitics.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 5+ years of circuit design experience or 7+ years in product engineering.
• Strong understanding of analog and digital circuit fundamentals and debugging.
• Experience with circuit simulation tools and methodologies.
• Knowledge of CMOS behavior, timing, and performance optimization.

Responsibilities

• Lead design and optimization of DRAM circuits including memory array, control logic, datapath, and test logic.
• Perform and analyze circuit simulations using tools such as SPICE and Verilog.
• Evaluate architectural trade-offs impacting power, performance, and die size.
• Integrate layout parasitics into simulations and drive design for manufacturability.
• Define validation strategies including test chip development and silicon bring-up.

Skills

Analog circuits

Digital circuits

Circuit debugging

SPICE simulations

Verilog

Design for manufacturability

Power and timing optimization

Collaboration across teams

Education

Bachelor's degree in Electrical Engineering or related field

Tools

SPICE

Verilog

Circuit simulation tools

Job description

Micron Technology, Inc. in Boise, Idaho, seeks a Staff DRAM Design Engineer to shape memory architectures and drive circuit innovations from concept to silicon bring-up.

You will lead design and optimization of DRAM circuits, and run SPICE and Verilog simulations. Collaborating with cross-functional teams across the globe, you will guide validation strategies, work on test chips, and contribute to manufacturability with layout parasitics.