SoC Verification Engineer - Hybrid, UVM/SV

Links Technology Solutions, Inc.; Carlsbad (CA); Hybrid; USD 96,000 - 110,000; Full time

Benefits offered by this job

Health insurance

Vision & dental

401K

Job summary

Links Technology Solutions, Inc. in Carlsbad, CA onsite/hybrid is seeking an ASIC Verification Engineer to develop UVM-based verification environments for next‑generation SoC designs.

You will create verification plans, build components like assertions and scoreboards, and work across teams to ensure testability and successful silicon bring‑up. Ideal candidates have 5–12 years of industry experience, expertise in SystemVerilog, C and Python, and familiarity with formal verification techniques.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• UVM-based testbench development experience.
• Experience in ASIC or SOC verification and test-plan delivery.

Responsibilities

• Develop and implement UVM-based verification environments.
• Create verification plans at block and system levels.
• Lead debug and collaborate to meet verification requirements.

Skills

UVM testbench

SystemVerilog

C programming

Python scripting

Education

Bachelor's degree in Electrical Engineering

Tools

RTL simulators

C/C++ toolchain

Job description

Links Technology Solutions, Inc. in Carlsbad, CA onsite/hybrid is seeking an ASIC Verification Engineer to develop UVM-based verification environments for next‑generation SoC designs.

You will create verification plans, build components like assertions and scoreboards, and work across teams to ensure testability and successful silicon bring‑up. Ideal candidates have 5–12 years of industry experience, expertise in SystemVerilog, C and Python, and familiarity with formal verification techniques.