Senior ASIC/SoC Verification Engineer (SystemVerilog & UVM)

Technical-Link N. America; San Diego (CA); Sur place; USD 120 000 - 180 000; Plein temps

Résumé du poste

Technical-Link N. America is seeking a Senior ASIC Verification Engineer with 8+ years of hands-on SystemVerilog and UVM experience to drive verification across IP, block, subsystem, and SoC levels. Satellite or DSP background is a plus but not required, and complex design debugging is essential.

The role emphasizes testbench development, scoreboards, reference models, and protocol monitors to ensure robust verification and signoff across multiple projects.

Qualifications

• Proficient in SystemVerilog and UVM verification across IP/Block/Subsystem/SoC levels.
• Experience in ASIC/SoC functional verification with testbench development.
• Strong skills in verification planning, assertions, and functional coverage closure.

Responsabilités

• Develop and maintain testbenches for IP/Block/Subsystem/SoC levels.
• Debug complex ASIC/SoC designs and drive verification to signoff.
• Create scoreboards, reference models, and protocol monitors for verification.
• Collaborate across teams on RTL debugging and datapath verification.

Connaissances

SystemVerilog

UVM

ASIC/SoC verification

Verification planning

Assertions

Functional coverage

Testbench development

Scoreboards

Reference models

Protocol monitors

RTL debugging

Datapath verification

Description du poste

Technical-Link N. America is seeking a Senior ASIC Verification Engineer with 8+ years of hands-on SystemVerilog and UVM experience to drive verification across IP, block, subsystem, and SoC levels. Satellite or DSP background is a plus but not required, and complex design debugging is essential.

The role emphasizes testbench development, scoreboards, reference models, and protocol monitors to ensure robust verification and signoff across multiple projects.