Design Verification Engineer

CloudIngest; California; On-site; USD 83,000 - 165,000; Full time

Job summary

CloudIngest is seeking a Design Verification Engineer to own pre-silicon functional verification of complex ASIC/SoC designs. You will translate specifications into verification plans and develop reusable SV/UVM environments, debugging RTL and testbench failures to drive coverage toward sign-off.

The role requires strong, hands-on UVM expertise, ownership of verification environments, and collaboration with RTL, firmware, and other teams to support the verification closure.

Qualifications

• 8+ years in ASIC/SoC verification, including 5+ years hands-on UVM development.
• Experience owning verification environments and computing coverage.
• Strong SystemVerilog/UVM expertise with testbench components and scoreboards.

Responsibilities

• Define verification scope from architecture specs and RTL to drive corner-case coverage.
• Develop reusable SV/UVM testbenches with agents, sequencers, drivers, monitors, and scoreboards.
• Create constrained-random and directed tests, virtual sequences, and UVM register models.
• Write SystemVerilog Assertions and functional coverage models.
• Execute regressions, triage failures, and analyze coverage gaps.
• Collaborate with RTL, firmware, and other teams to sign-off verification.

Skills

UVM expertise

Verification planning

RTL debugging

Problem solving

Communication

Education

Bachelor's/Master in EE/CE

Tools

SystemVerilog/UVM

Linux/Unix

Python scripting

Job description

Job Title: Design Verification Engineer — SystemVerilog/UVM

Location: Sunnyvale, CA — Onsite Work, 5 days/week in the office

Employment Type: Contract Opportunity — Initial contract of a 12-month term, with extensions.

MUST-HAVE Experience

Minimum 8+ years in ASIC/SoC verification, including 5+ years of hands-on UVM development

Role Overview

• We are seeking a Design Verification Engineer to own pre-silicon functional verification of complex ASIC/SoC designs. The engineer will translate design specifications into verification plans, develop reusable SystemVerilog/UVM environments, debug RTL and testbench failures, and drive verification coverage toward sign-off.
• Strong, hands-on UVM expertise is mandatory. Candidates must demonstrate practical experience developing and debugging verification environments, including testbench components, stimulus, checking mechanisms, and coverage models.

Key Responsibilities

• Review architecture specifications, microarchitecture documents, and RTL to define verification scope, risks, and corner cases.
• Develop verification strategies, detailed test plans, and measurable coverage goals for IP, subsystem, or SoC designs.
• Architect, develop, and maintain reusable SystemVerilog/UVM testbenches, including agents, sequencers, drivers, monitors, scoreboards, and reference models.
• Develop constrained-random and directed tests, virtual sequences, protocol checkers, and UVM register models.
• Write SystemVerilog Assertions and functional coverage models to verify design behavior and protocol compliance.
• Execute regressions, triage failures, and identify root causes across RTL, verification infrastructure, and test stimulus.
• Analyze functional and code coverage, develop targeted tests, and resolve coverage gaps.
• Collaborate with RTL designers, architects, firmware engineers, and other verification teams to resolve issues and support verification sign-off.
• Improve regression workflows, debug efficiency, and reporting through scripting and automation.

Required Qualifications and Experience

• A technically strong engineer who can independently take a design block or subsystem from specification review through verification closure, explain the UVM infrastructure they personally developed, and demonstrate effective RTL debugging and coverage-driven verification.
• Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or a related discipline, or equivalent practical experience.
• 8+ years of relevant ASIC/SoC design verification experience.
• 5+ years of hands-on SystemVerilog/UVM development, with demonstrable ownership of verification environments.
• Strong understanding of UVM architecture, phases, factory mechanisms, configuration database, TLM communication, objections, and sequence execution.
• Experience developing reusable testbench components, scoreboards, functional coverage, and register-level verification using UVM RAL.
• Strong knowledge of digital design, RTL behavior, constrained-random verification, and assertion-based verification using SVA.
• Experience creating verification plans and driving regression debugging and coverage closure.
• Proficiency with at least one major simulation platform: Synopsys VCS, Cadence Xcelium, or Siemens Questa.
• Strong waveform-debugging, analytical, communication, and independent problem-solving skills.
• Working knowledge of Linux/Unix and scripting with Python, Perl, Tcl, or shell.

Preferred Skills (big plus)

• Verification ownership through tape-out on one or more ASIC/SoC programs.
• Experience with one or more relevant interfaces: PCIe, DDR/LPDDR, Ethernet, USB, or AMBA AXI/AHB/APB.
• Experience verifying CPUs, GPUs, AI/ML accelerators, memory subsystems, interconnects, or cache-coherent systems.
• Familiarity with ARM or RISC-V architectures.
• Experience with low-power verification using UPF, gate-level simulation, formal verification, or emulation.
• Experience developing verification IP or integrating third-party VIP.