SoC Verification Engineer: Build Cutting-Edge UVM Environments

UST; Mountain View (CA); On-site; USD 101,000 - 152,000; Full time

Benefits offered by this job

Paid vacation and sick leave

Paid holidays

401(k) Retirement Plan with employer 


Health insurance (medical, dental, and

Job summary

UST is seeking two experienced SoC Design Verification Engineers to own functional and performance verification for complex System-on-Chip designs in Mountain View, CA. You will build UVM-based verification environments, develop test benches, and create coverage models that drive quality before silicon.

Collaboration with design and architecture teams is essential. Ideal candidates have 3–5 years of SoC verification, strong SystemVerilog/UVM skills, and proficiency in Python/C++.

Qualifications

• 3-5 years of SoC verification experience, including SoC-level functional and performance verification.
• Bachelor's or master's degree in electrical engineering, computer engineering, or a related field.
• Strong understanding of digital design principles and SoC architecture.
• Proficiency in SystemVerilog and UVM for building verification environments.
• Proficiency in Python and C/C++ for scripting and test development.
• Hands-on experience with simulation tools such as Synopsys VCS or Cadence Xcelium, including debugging simulation results.

Responsibilities

• Develop and execute verification plans for complex SoC designs, covering functional and performance verification at the core and SoC levels.
• Perform functional and performance verification using simulation, emulation, and formal verification techniques.
• Create and maintain UVM-based verification environments, test benches, test cases, and coverage models in SystemVerilog and C++.
• Run regressions in Synopsys VCS or Cadence Xcelium, and debug and analyze simulation results to isolate and resolve design issues.
• Review design specifications and architecture with design teams to identify verification challenges early in the development cycle.
• Develop Python and C/C++ scripts to automate verification flows and results analysis.
• Document verification results, track coverage and progress, and participate in code reviews to improve verification methodologies.

Skills

C

C++

SystemVerilog

UVM

SoC Architecture

Emulation

AHB

AXI

Cadence Xcelium

Coverage Modeling

DDR

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Master's degree in Electrical Engineering or Computer Engineering

Tools

Cadence Xcelium

Job description

UST is seeking two experienced SoC Design Verification Engineers to own functional and performance verification for complex System-on-Chip designs in Mountain View, CA. You will build UVM-based verification environments, develop test benches, and create coverage models that drive quality before silicon.

Collaboration with design and architecture teams is essential. Ideal candidates have 3–5 years of SoC verification, strong SystemVerilog/UVM skills, and proficiency in Python/C++.