Senior SOC Verification & Methodology Engineer

QUALCOMM, Inc.; San Diego (CA); On-site; USD 174,000 - 262,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking an experienced ASIC Design Verification Engineer to validate System-on-Chip designs and drive verification across IPs and system-level integration.

You will develop verification plans, implement test benches, and debug complex issues using advanced methodologies in a globally distributed team. The role requires strong SystemVerilog/UVM skills, experience from test planning to tapeout, and collaboration with architects and verification teams to ensure

Qualifications

• Bachelor’s degree in science or engineering with 6+ years of ASIC design, verification, validation, integration experience.
• Strong SystemVerilog/UVM verification with assertion and coverage-based methods.
• Experience from test planning to tapeout for large-scale HW designs.

Responsibilities

• Develop verification plans and define verification scope from design specs.
• Develop test plans and verification infrastructure.
• Execute verification tests and debug complex issues; implement assertions and coverage checks.
• Collaborate with architects, designers, and pre-/post-silicon teams to deliver results.
• Ramp up on new DV tools and methodologies; push quality and efficiency of test benches.

Skills

UVM-based verification

SystemVerilog

Test planning

Debugging

Python

Perl

ARM knowledge

Pre-silicon emulation

Formal verification tools

Education

Bachelor’s degree in science/engineering

Master’s degree in science/engineering

PhD in science/engineering

Tools

Pre-silicon emulation

Emulation platforms

SystemVerilog simulators

Job description

Qualcomm Technologies, Inc. is seeking an experienced ASIC Design Verification Engineer to validate System-on-Chip designs and drive verification across IPs and system-level integration.

You will develop verification plans, implement test benches, and debug complex issues using advanced methodologies in a globally distributed team. The role requires strong SystemVerilog/UVM skills, experience from test planning to tapeout, and collaboration with architects and verification teams to ensure