Hybrid ASIC Verification Engineer for Networking SoCs

Hewlett Packard Enterprise; Sunnyvale (CA); Hybrid; USD 120,000 - 243,000; Full time

Job summary

Hewlett Packard Enterprise Development LP in Sunnyvale, CA is seeking a highly motivated ASIC Verification Engineer for a Hybrid role requiring 2 days per week in-office. You will drive block- and subsystem-level verification for high-speed networking ASICs, building and maintaining UVM environments, and delivering thorough coverage and debug capabilities.

Ideal candidates have 5+ years in ASIC/SoC verification, strong SystemVerilog/UVM proficiency, and hands-on testing, debugging, and coverage

Qualifications

• 5+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.
• Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.
• Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
• Hands‑on experience in test planning, coverage analysis, and debugging of complex SoC designs.
• Proficiency with industry-standard simulation tools (Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging.

Responsibilities

• Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.
• Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
• Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
• Analyze simulation results using industry-leading simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and debug waveforms to validate design functionality.
• Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables.

Skills

5+ years of experience in ASIC/SoC ver

SystemVerilog and UVM

Randomization & constraints

Test planning & coverage analysis

Cadence Xcelium, Synopsys VCS, Mentor/

Tools

Cadence Xcelium

Synopsys VCS

Mentor Questa

Job description

Hewlett Packard Enterprise Development LP in Sunnyvale, CA is seeking a highly motivated ASIC Verification Engineer for a Hybrid role requiring 2 days per week in-office. You will drive block- and subsystem-level verification for high-speed networking ASICs, building and maintaining UVM environments, and delivering thorough coverage and debug capabilities.

Ideal candidates have 5+ years in ASIC/SoC verification, strong SystemVerilog/UVM proficiency, and hands-on testing, debugging, and coverage