Design Verification Engineer - SystemVerilog/UVM (Onsite)

CloudIngest; California; On-site; USD 83,000 - 165,000; Full time

Job summary

CloudIngest is seeking a Design Verification Engineer to own pre-silicon functional verification of complex ASIC/SoC designs. You will translate specifications into verification plans and develop reusable SV/UVM environments, debugging RTL and testbench failures to drive coverage toward sign-off.

The role requires strong, hands-on UVM expertise, ownership of verification environments, and collaboration with RTL, firmware, and other teams to support the verification closure.

Qualifications

• 8+ years in ASIC/SoC verification, including 5+ years hands-on UVM development.
• Experience owning verification environments and computing coverage.
• Strong SystemVerilog/UVM expertise with testbench components and scoreboards.

Responsibilities

• Define verification scope from architecture specs and RTL to drive corner-case coverage.
• Develop reusable SV/UVM testbenches with agents, sequencers, drivers, monitors, and scoreboards.
• Create constrained-random and directed tests, virtual sequences, and UVM register models.
• Write SystemVerilog Assertions and functional coverage models.
• Execute regressions, triage failures, and analyze coverage gaps.
• Collaborate with RTL, firmware, and other teams to sign-off verification.

Skills

UVM expertise

Verification planning

RTL debugging

Problem solving

Communication

Education

Bachelor's/Master in EE/CE

Tools

SystemVerilog/UVM

Linux/Unix

Python scripting

Job description

CloudIngest is seeking a Design Verification Engineer to own pre-silicon functional verification of complex ASIC/SoC designs. You will translate specifications into verification plans and develop reusable SV/UVM environments, debugging RTL and testbench failures to drive coverage toward sign-off.

The role requires strong, hands-on UVM expertise, ownership of verification environments, and collaboration with RTL, firmware, and other teams to support the verification closure.