Senior ASIC/SoC Verification Engineer — UVM, SystemVerilog

Insight Global; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Insight Global seeks a Design Verification Engineer to join Cisco's silicon one group in San Jose, CA. You will develop UVM-based verification environments and create comprehensive verification plans across block and system levels.

You’ll design assertions, traffic generators, agents and scoreboards, collaborate with cross-functional teams to assess testability, and lead debugging efforts for complex challenges.

Qualifications

• UVM-based verification experience and testbench development.
• Experience in ASIC or SOC verification and test plan development.
• Familiarity with verification methodologies from block to system level.

Responsibilities

• Develop and implement UVM verification environments.
• Create verification plans at block and system levels.
• Design assertions, traffic generators, agents and scoreboards.
• Collaborate on testability needs and verification requirements.
• Lead debug efforts and propose solutions for complex issues.

Skills

UVM testbench development

Test plans development

ASIC/SoC verification

Debugging complex tech

End-to-end verification methodology

AI-based CAD efficiency ideas

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Python

Perl

SystemVerilog

C programming

Formal verification techniques

UCIe/PCIe knowledge

Job description

Insight Global seeks a Design Verification Engineer to join Cisco's silicon one group in San Jose, CA. You will develop UVM-based verification environments and create comprehensive verification plans across block and system levels.

You’ll design assertions, traffic generators, agents and scoreboards, collaborate with cross-functional teams to assess testability, and lead debugging efforts for complex challenges.