SoC Physical Design Engineer - 7+ yrs, On-Site

Arrow Enterprise Computing Solutions; San Jose (CA); On-site; USD 170,000 - 210,000; Full time

Benefits offered by this job

Medical, Dental, Vision Insurance

401k, With Matching Contributions

Short-Term/Long-Term Disability

HSAs/HRA Options

Paid Time Off

Tuition Reimbursement

Growth Opportunities

On-site work

Job summary

eInfochips, an Arrow company, seeks a Physical Design Engineer to execute synthesis, PNR, and STA for ASIC blocks and collaborate with architects, RTL designers, and DFT engineers. You will drive signoff for EM/IR, LEC, and PDN, coordinating with methodology owners to resolve issues.

Strong TCL scripting is required. The role requires 7+ years of physical design experience, proficiency with Innovus/Tempus/Quantus, and hands-on SoC design expertise at sub-7nm nodes in a fully on-site San Jose, CA

Qualifications

• Bachelor's degree in electrical engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
• 7+ years of hands‑on experience in physical design and implementation, encompassing synthesis, PnR, timing convergence and physical verification.
• Proficiency in utilizing Electronic Design Automation (EDA) tools such as Innovus, Tempus, and Quantus, as well as a deep understanding of physical design flows and methodologies.
• 7+ years of experience in physical design roles and related activities.
• Proven ability to adhere to tight schedules and implement low-power design techniques.
• Experience in System-on-Chip (SoC) design and implementation.
• Expertise in sub-7nm node technologies.
• Familiarity with industry-standard EDA tools and their capabilities.
• Strong scripting skills in TCL to develop custom flows and methodologies on standard EDA tools from Cadence/Synopsys.

Responsibilities

• Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.
• Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
• Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
• Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence.
• Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC).
• Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed.

Skills

Physical design

Synthesis/PNR/STA

SoC design

EDA tools (Innovus/Tempus/Quantus)

TCL scripting

Education

Bachelor's degree in electrical/computer engineering or related field

Tools

Innovus

Tempus

Quantus

Job description

eInfochips, an Arrow company, seeks a Physical Design Engineer to execute synthesis, PNR, and STA for ASIC blocks and collaborate with architects, RTL designers, and DFT engineers. You will drive signoff for EM/IR, LEC, and PDN, coordinating with methodology owners to resolve issues.

Strong TCL scripting is required. The role requires 7+ years of physical design experience, proficiency with Innovus/Tempus/Quantus, and hands-on SoC design expertise at sub-7nm nodes in a fully on-site San Jose, CA