Senior SoC Physical Design Engineer — Sub-7nm, On-Site SJ

Arrow Electronics; Austin (TX); On-site; USD 140,000 - 170,000; Full time

Benefits offered by this job

Medical, Dental, Vision Insurance

401k with Matching Contributions

Paid Time Off

Job summary

Arrow Electronics (eInfochips) is seeking a Physcial Design Engineer to execute synthesis, PNR, and STA for ASIC partitions, coordinating with architects and RTL/DFT teams to meet tight schedules.

The role requires 7+ years in physical design, proficiency with Innovus/Tempus/Quantus, and strong TCL scripting for custom flows on CAD tools. On-site at customer locations, with a broad benefits package.

Qualifications

• Bachelor’s degree or equivalent in electrical/computer engineering or related field.
• 7+ years of hands-on physical design experience including synthesis, PnR, timing convergence and physical verification.
• Proficient with EDA tools such as Innovus, Tempus, Quantus; strong knowledge of PD flows and methodologies.

Responsibilities

• Execute synthesis, PNR, and STA for assigned ASIC partitions.
• Collaborate with architects, RTL, and DFT to resolve issues and signoffs.
• Address EM/IR, drive LEC and physical verification signoff with method owners.

Skills

Synthesis/PNR/STA

Physical design flow

EDAs tools

TCL scripting

SoC design

Education

Bachelor’s degree in EE/CE/CS

Tools

Innovus

Tempus

Quantus

Cadence/Synopsys

Job description

Arrow Electronics (eInfochips) is seeking a Physcial Design Engineer to execute synthesis, PNR, and STA for ASIC partitions, coordinating with architects and RTL/DFT teams to meet tight schedules.

The role requires 7+ years in physical design, proficiency with Innovus/Tempus/Quantus, and strong TCL scripting for custom flows on CAD tools. On-site at customer locations, with a broad benefits package.