Senior Physical Design Engineer – SoC, Sub-7nm, On-Site

Arrow Enterprise Computing Solutions; San Jose (CA); On-site; USD 150,000 - 200,000; Full time

Benefits offered by this job

Medical, Dental, Vision Insurance

401k with matching contributions

Disability Insurance

HSA/HRA options

Paid time off

Job summary

Arrow Enterprise Computing Solutions in San Jose, CA is seeking a Physical Design Engineer II for ASIC partitions. You will drive synthesis, PnR, and STA while collaborating with architects, RTL designers, and DFT engineers to meet strict schedules and design goals.

Applicants should have a bachelor’s in Electrical/Computer Engineering or related field and 7+ years of hands-on physical design experience, with proficiency in Innovus, Tempus, and Quantus.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
• 7+ years of hands-on experience in physical design and implementation, including synthesis, PnR, timing convergence and physical verification.
• Proficiency with EDA tools such as Innovus, Tempus, and Quantus; deep understanding of physical design flows.

Responsibilities

• Execute synthesis, PNR, and STA for assigned partitions of ASIC chips.
• Collaborate with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues.
• Close EM/IR, drive LEC and physical verification signoff for partitions with methodology owners.
• Partner with the design team to address physical design challenges and enable efficient iteration.
• Refine implementation methodologies, including EMIR, PDN, and TCL scripting for standard tools.

Skills

Synthesis & PnR

Timing convergence

Physical verification

LEC

EM/IR mitigation

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Tools

Innovus

Tempus

Quantus

Job description

Arrow Enterprise Computing Solutions in San Jose, CA is seeking a Physical Design Engineer II for ASIC partitions. You will drive synthesis, PnR, and STA while collaborating with architects, RTL designers, and DFT engineers to meet strict schedules and design goals.

Applicants should have a bachelor’s in Electrical/Computer Engineering or related field and 7+ years of hands-on physical design experience, with proficiency in Innovus, Tempus, and Quantus.