Senior Physical Design Engineer II, SoC (sub-7nm)

Uncrewed Engineering Jobs; San Jose (CA); In loco; USD 180.000 - 240.000; Tempo pieno

Vantaggi offerti da questo lavoro

Medical, Dental, Vision Insurance

401k with matching

Paid Time Off

Tuition Reimbursement

Growth opportunities

Descrizione del lavoro

Arrow in San Jose, California is seeking a senior ASIC physical design engineer to execute synthesis, PnR, and STA for assigned partitions of an SoC under strict schedules. You will collaborate with architects, RTL designers, and DFT teams to resolve issues, drive EM/IR, LEC signoffs, and ensure low-power design techniques while refining flow methodologies and addressing flow issues with EDA vendors.

You will contribute to the refinement of implementation methodologies, ensuring convergence and

Competenze

• Bachelor’s degree in electrical engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
• 7+ years of hands-on experience in physical design and implementation, encompassing synthesis, PnR, timing convergence and physical verification.
• Proficiency in utilizing Electronic Design Automation (EDA) tools such as Innovus, Tempus, and Quantus, as well as a deep understanding of physical design flows and methodologies.
• 7+ years of experience in physical design roles and related activities.
• Proven ability to adhere to tight schedules and implement low‑power design techniques.
• Experience in System-on-Chip (SoC) design and implementation.
• Expertise in sub‑7nm node technologies.
• Familiarity with industry‑standard EDA tools and their capabilities.
• Strong scripting skills in TCL to develop custom flows and methodologies on standard EDA tools from Cadence/Synopsys.

Mansioni

• Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.
• Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
• Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
• Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence.
• Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC).
• Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed.

Conoscenze

Physical design

Synthesis

PnR

Timing convergence

SoC design

Low-power

EM/IR

TCL scripting

EDA tools

Formazione

Bachelor's degree in Electrical Engineering or related field

Strumenti

Innovus

Tempus

Quantus

Cadence/Synopsys tools

TCL scripting

Descrizione del lavoro

Arrow in San Jose, California is seeking a senior ASIC physical design engineer to execute synthesis, PnR, and STA for assigned partitions of an SoC under strict schedules. You will collaborate with architects, RTL designers, and DFT teams to resolve issues, drive EM/IR, LEC signoffs, and ensure low-power design techniques while refining flow methodologies and addressing flow issues with EDA vendors.

You will contribute to the refinement of implementation methodologies, ensuring convergence and