Senior Physical Design Engineer — SoC/Sub-7nm Expert

eInfochips (An Arrow Company); San Jose (CA); On-site; USD 130,000 - 170,000; Full time

Benefits offered by this job

401k with matching contributions

Disability Insurance

Health Savings Account (HSA) / Health)

Tuition Reimbursement

And more!

Job summary

eInfochips, an Arrow company, seeks an experienced physical design engineer to drive synthesis, PnR, and timing convergence for ASIC partitions on-site in San Jose, CA. You will work with architects, RTL, and DFT teams to ensure design signoffs and address EM/IR challenges.

Preferred candidates have 7+ years in SoC physical design, deep PD flows, and proficiency with Innovus and Genus. This role emphasizes tight schedules and collaboration with EDA vendors.

Qualifications

• Bachelor's degree or equivalent practical experience in a technical field.
• 7+ years hands-on experience in physical design and implementation including synthesis, PnR, timing convergence and physical verification.

Responsibilities

• Execute synthesis, PNR, and STA for assigned partitions of ASIC chip within schedules and goals.
• Collaborate with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues.
• Close EM/IR, drive LEC and physical verification signoff for partitions with methodology owners.
• Partner with design team to address physical design challenges for efficient iteration and convergence.
• Refine implementation methodologies including EMIR, PDN, and LEC, and troubleshoot flow issues with EDA vendors.

Skills

Synthesis

PnR

Timing convergence

Physical verification

Innovus

Genus

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Innovus

Genus

Job description

eInfochips, an Arrow company, seeks an experienced physical design engineer to drive synthesis, PnR, and timing convergence for ASIC partitions on-site in San Jose, CA. You will work with architects, RTL, and DFT teams to ensure design signoffs and address EM/IR challenges.

Preferred candidates have 7+ years in SoC physical design, deep PD flows, and proficiency with Innovus and Genus. This role emphasizes tight schedules and collaboration with EDA vendors.