Senior Physical Design Engineer, SoC & PnR Expert

Fortell; San Jose (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Fortell in California is seeking an experienced ASIC Physical Design Engineer to drive chip implementation from synthesis through signoff, partnering with architects, RTL designers, and DFT engineers. You will ensure power-aware convergence, meet strict schedules, and lead verification signoffs across partitions.

This role requires 7+ years in physical design, fluency with Innovus/Tempus/Quantus, and strong TCL scripting to optimize flows and reduce risk across SoC implementations.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, CS, or related field.
• 7+ years hands-on experience in physical design, synthesis, PnR, timing convergence and physical verification.
• Proficiency with EDA tools (Innovus, Tempus, Quantus) and deep understanding of physical design flows.

Responsibilities

• Execute synthesis, PNR, and STA for assigned ASIC partitions with tight schedules.
• Collaborate with architects, RTL, and DFT teams to resolve design issues.
• Close EM/IR and drive LEC/physical verification signoff for partitions.
• Partner with design teams to address physical design challenges for efficient convergence.
• Refine implementation methodologies across PnR, EM/IR, PDN and LEC flows.
• Troubleshoot flow issues and coordinate with EDA vendors as needed.

Skills

Synthesis

PnR

Physical verification

Timing convergence

EM/IR

TCL scripting

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field

Tools

Innovus

Tempus

Quantus

Cadence/Synopsys TCL scripting

Job description

Fortell in California is seeking an experienced ASIC Physical Design Engineer to drive chip implementation from synthesis through signoff, partnering with architects, RTL designers, and DFT engineers. You will ensure power-aware convergence, meet strict schedules, and lead verification signoffs across partitions.

This role requires 7+ years in physical design, fluency with Innovus/Tempus/Quantus, and strong TCL scripting to optimize flows and reduce risk across SoC implementations.