Senior Physical Design Engineer - SoC (Sub-7nm), On-Site

Arrow Enterprise Computing Solutions; San Jose (CA); On-site; USD 112,000 - 193,000; Full time

Benefits offered by this job

Medical, Dental, Vision Insurance

401k with Matching Contributions

Disability Insurance

HSA/HRA Options

Paid Time Off

Tuition Reimbursement

Growth Opportunities

Job summary

Arrow Enterprise Computing Solutions seeks a Senior Physical Design Engineer for on-site work in San Jose, CA. You will execute synthesis, place and route, and timing convergence for ASIC partitions, collaborating with architects, RTL, and DFT teams to close signoffs.

Must have 10+ years in physical design, expertise with SoC design, sub-7nm tech, and strong TCL scripting to automate flows. EDA tool proficiency is essential.

Qualifications

• Bachelor's degree in EE/CE/CS or equivalent.
• 10+ years in physical design, synthesis, PnR, timing convergence.
• Strong EDA tool experience with Innovus, Tempus and Quantus.
• SoC design experience and sub-7nm knowledge.
• Proficient TCL scripting for custom flows.

Responsibilities

• Execute synthesis, PNR, and STA for assigned ASIC partitions.
• Collaborate with architects, RTL designers, and DFT engineers to resolve issues.
• Close EM/IR, drive LEC and physical verification signoff.
• Address physical design challenges and iterate flows.
• Refine PD/SoC methodologies including EM/IR, PDN, and LEC.
• Troubleshoot flow issues and coordinate with EDA vendors.

Skills

Physical design

Timing convergence

Low-power design

SoC design experience

TCL scripting

EDA tool proficiency

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Innovus

Tempus

Quantus

Cadence/Synopsys flows

Job description

Arrow Enterprise Computing Solutions seeks a Senior Physical Design Engineer for on-site work in San Jose, CA. You will execute synthesis, place and route, and timing convergence for ASIC partitions, collaborating with architects, RTL, and DFT teams to close signoffs.

Must have 10+ years in physical design, expertise with SoC design, sub-7nm tech, and strong TCL scripting to automate flows. EDA tool proficiency is essential.