Silicon Design Lead for RTL ML Accelerators

Google Inc.; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Benefits offered by this job

Equity grants

Job summary

Google Inc. Sunnyvale, CA is seeking a Silicon Design Manager for RTL Machine Learning and Accelerator Design to shape the future of AI/ML hardware acceleration.

You will drive TPU architecture and verification, leading a team to deliver high-performance, low-power IP for compute cores and integration with software teams. The role emphasizes architectural feasibility, timing goals, and trade-offs for physical design closure, with cross-functional collaboration across Verification, DFT, Physical

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 10 years of experience with Chip Design, ASIC Digital Design, and SystemVerilog.
• 8 years of experience in Computer Architecture and Register-Transfer Level.
• 3 years of experience in people management and developing employees.

Responsibilities

• Lead, mentor, and manage RTL design engineers performing tasks related to IP development for Compute Cores.
• Provide technical leadership to engineers and model best design practices (i.e., micro-architecture specifications, design reviews, code reviews, design methodology).
• Serve as the primary point of contact for all design-related activities on projects. Participate with Architecture and System Design teams in architecture definition, IP area estimation, power optimization, and performance enhancements.
• Collaborate closely with cross-functional teams (e.g., Verification, Design for Test, Physical Design, and Software) to make design plans and present project status throughout the development cycle.
• Drive improvements in design methodologies, processes, and quality control measures.

Skills

People management

SystemVerilog

RTL design

ASIC design

Education

Bachelor's degree in Electrical/Computer Engineering or CS

Master's or PhD in EE/CE/CS (preferred)

Tools

DFT

Synthesis

STA

Physical Design

Verification

Job description

Google Inc. Sunnyvale, CA is seeking a Silicon Design Manager for RTL Machine Learning and Accelerator Design to shape the future of AI/ML hardware acceleration.

You will drive TPU architecture and verification, leading a team to deliver high-performance, low-power IP for compute cores and integration with software teams. The role emphasizes architectural feasibility, timing goals, and trade-offs for physical design closure, with cross-functional collaboration across Verification, DFT, Physical