Senior VLSI Verification Engineer — UVM/SystemVerilog

Oho Group Ltd; Austin (TX); On-site; USD 100,000 - 140,000; Full time

Benefits offered by this job

Compelling equity options

Job summary

A company specializing in advanced technology solutions in Austin is seeking a Senior Verification Engineer with over 10 years of experience. The ideal candidate will have strong expertise in VLSI verification, proficiency in UVM and SystemVerilog, and hands-on experience across multiple verification cycles. This full-time position offers exciting opportunities within well-backed startups and is not suitable for entry-level candidates.

Qualifications

• 10+ years of experience in the semiconductor industry.
• Strong proficiency in VLSI verification processes.
• Hands-on experience in multiple full block or system verification cycles.

Responsibilities

• Lead VLSI verification efforts for complex projects.
• Collaborate effectively with cross-functional teams to deliver solutions.

Skills

VLSI verification

UVM

SystemVerilog

Collaboration with cross-functional teams

Job description

A company specializing in advanced technology solutions in Austin is seeking a Senior Verification Engineer with over 10 years of experience. The ideal candidate will have strong expertise in VLSI verification, proficiency in UVM and SystemVerilog, and hands-on experience across multiple verification cycles. This full-time position offers exciting opportunities within well-backed startups and is not suitable for entry-level candidates.