Senior Verification Engineer: VLSI/UVM, SV (Austin)

5 Star Recruitment; Austin (TX); On-site; USD 100,000 - 130,000; Full time

Job summary

A recruitment agency seeks a Senior Verification Engineer in Austin, TX. You will plan and perform verification of digital design blocks, build environments using SystemVerilog and UVM, and work closely with design engineers. Applicants should have at least 6 years of experience and in-depth knowledge of verification flows, preferably with experience in Ethernet protocols. This position requires on-site work five days a week.

Qualifications

• 6+ years of experience required.
• Experience with full block/system verification cycles.
• In depth knowledge of VLSI verification flow, languages and concepts.

Responsibilities

• Plan and perform verification of digital design blocks.
• Build verification environments using SystemVerilog and UVM.
• Identify and write coverage measures.

Skills

VLSI verification flow

SystemVerilog

UVM

Debugging

Data protocols (Ethernet)

Job description

A recruitment agency seeks a Senior Verification Engineer in Austin, TX. You will plan and perform verification of digital design blocks, build environments using SystemVerilog and UVM, and work closely with design engineers. Applicants should have at least 6 years of experience and in-depth knowledge of verification flows, preferably with experience in Ethernet protocols. This position requires on-site work five days a week.