Senior Verification Engineer

5 Star Recruitment; Austin (TX); Presencial; USD 100.000 - 130.000; Jornada completa

Descripción de la vacante

A recruitment agency seeks a Senior Verification Engineer in Austin, TX. You will plan and perform verification of digital design blocks, build environments using SystemVerilog and UVM, and work closely with design engineers. Applicants should have at least 6 years of experience and in-depth knowledge of verification flows, preferably with experience in Ethernet protocols. This position requires on-site work five days a week.

Formación

• 6+ years of experience required.
• Experience with full block/system verification cycles.
• In depth knowledge of VLSI verification flow, languages and concepts.

Responsabilidades

• Plan and perform verification of digital design blocks.
• Build verification environments using SystemVerilog and UVM.
• Identify and write coverage measures.

Conocimientos

VLSI verification flow

SystemVerilog

UVM

Debugging

Data protocols (Ethernet)

Descripción del empleo

About the job Senior Verification Engineer

Requirements

• 6+ years of experience a must
• Performed at last 2 or more full block/system verification cycles.
• In depth knowledge in VLSI verification flow, languages and concepts.
• Experience in data path or data protocols, specifically Ethernet - preferred
• Verification using one of the known methodologies (eRM, UVM, OVM).

Responsibilities

• Plan and perform the verification of digital design blocks according to the design specification and interacting with design engineers.
• Build verification environments using SystemVerilog and UVM.
• Identify and write all types of coverage measures for corner-cases.
• Debug the functionality with design engineers.
• Perform coverage collection and follow the metrices to close the full functionality.

Required Citizenship / Work Permit / Visa StatusWill sponsor H1-B

Must-Haves

• On-site in Austin, TX, five days a week.
• Performed at least 2 or more full block/system verification cycles.
• In depth knowledge in VLSI verification flow, languages and concepts.