A leading technology firm in California is looking for a highly experienced engineer specializing in the verification of complex System-on-Chip (SoC) designs. The ideal candidate will have over 12 years of experience using advanced verification methodologies, including System Verilog and UVM. Key responsibilities include developing reusable test benches, collaborating with diverse teams, and mentoring junior members. Competitive compensation includes a range of $91,000 - $232,000 and benefits from day one.
Qualifications
12+ years in functional verification of complex SoC designs.
Expertise in System Verilog, UVM, formal verification methodologies.
Proven experience in methodology development and tool automation.
Responsibilities
Verification of complex subsystems and SoC using verification methodologies.
Develop and maintain UVM-based test benches and environments.
Collaborate with architecture and design teams for successful execution.
Skills
Functional verification of complex SoC designs
System Verilog
UVM
Formal verification methodologies
AI/ML-driven EDA tools
Scripting in Python
Scripting in TCL/TK
C/C++ automation
Excellent debug skills
Collaboration skills
Education
BS or MS in Electrical/Electronic Engineering
Tools
Siemens verification suites
Cadence verification suites
Synopsys verification suites
Revision control systems (Git, Perforce, svn)
Job description
A leading technology firm in California is looking for a highly experienced engineer specializing in the verification of complex System-on-Chip (SoC) designs. The ideal candidate will have over 12 years of experience using advanced verification methodologies, including System Verilog and UVM. Key responsibilities include developing reusable test benches, collaborating with diverse teams, and mentoring junior members. Competitive compensation includes a range of $91,000 - $232,000 and benefits from day one.