Lead VCS Verification Engineer (UVM, Debug & Deployment)

Synopsys Inc; Austin (TX); Presencial; USD 120.000 - 180.000; Jornada completa

Descripción de la vacante

Synopsys Inc. is seeking an experienced Verification Engineer in Austin to lead VCS deployments and work closely with design and verification teams to integrate cutting-edge simulation tooling into their flows.

You will diagnose complex issues, optimize performance, and translate customer feedback into actionable product requirements. You will leverage SystemVerilog, UVM, SVA, Verilog and VHDL to debug and validate testbenches, and collaborate with R&D on improvements.

Formación

• Bachelor's in Electronics or Computer Engineering required; Master's preferred.
• Strong hands-on experience with simulation technologies (VCS or equivalents).
• Proficiency in SystemVerilog, UVM, SVA, Verilog, and VHDL; read and debug complex testbenches.

Responsabilidades

• Lead VCS simulation deployments at customer sites, integrating the tool into existing flows and resolving adoption blockers.
• Diagnose complex simulation mismatches, performance bottlenecks, and verification environment issues using VCS, Verdi, and debugging infrastructure.
• Translate customer pain points into actionable product requirements and validate fixes in real customer environments.
• Drive competitive evaluations and benchmarking engagements to demonstrate VCS capabilities.
• Develop automation scripts in Perl, TCL, Shell, and Make to streamline workflows and improve throughput.
• Interface with product validation and R&D teams to propose improvements in simulation accuracy, performance, and usability.
• Support customers using advanced verification methodologies including UVM, SVA, low-power simulation, gate-level verification, and functional safety flows.

Conocimientos

Verification engineering

UVM

SystemVerilog

SVA

Verilog

VHDL

Debugging

Educación

Bachelor's in Electronics or Computer Engineering

Master's degree (preferred)

Herramientas

VCS

Verdi

UNIX/Linux

Descripción del empleo

Synopsys Inc. is seeking an experienced Verification Engineer in Austin to lead VCS deployments and work closely with design and verification teams to integrate cutting-edge simulation tooling into their flows.

You will diagnose complex issues, optimize performance, and translate customer feedback into actionable product requirements. You will leverage SystemVerilog, UVM, SVA, Verilog and VHDL to debug and validate testbenches, and collaborate with R&D on improvements.