Senior ASIC Verification Engineer - UVM & SystemVerilog

Mogi I/O : OTT/Podcast/Short Video Apps for you; Bastrop (TX); On-site; USD 160,000 - 180,000; Full time

Job summary

A technology firm is looking for a Verification Engineer to lead RTL design verification for high-speed digital systems. The ideal candidate should have extensive experience in developing verification plans and a strong command of SystemVerilog and UVM. They will be responsible for executing test strategies, defining functional coverage, and collaborating closely with design teams. This role offers competitive compensation in a dynamic environment.

Qualifications

• 5+ years in digital/RTL engineering.
• 3+ years in design verification.
• Strong knowledge of VLSI verification flows.

Responsibilities

• Develop and execute verification plans based on design specs.
• Build and maintain SV/UVM environments.
• Define and close functional and code coverage.

Skills

Digital/RTL engineering experience

Design verification

VLSI verification flows

SystemVerilog

UVM

Debugging skills

Job description

A technology firm is looking for a Verification Engineer to lead RTL design verification for high-speed digital systems. The ideal candidate should have extensive experience in developing verification plans and a strong command of SystemVerilog and UVM. They will be responsible for executing test strategies, defining functional coverage, and collaborating closely with design teams. This role offers competitive compensation in a dynamic environment.