Senior Design Verification Engineer - SystemVerilog/UVM

Themesoft Inc.; Austin (TX); On-site; USD 120,000 - 150,000; Full time

Job summary

Themesoft Inc. is seeking an experienced verification engineer based in Austin, TX. The ideal candidate will have over 8 years of experience, particularly in architecting and developing complex verification environments using SystemVerilog. Responsibilities include writing tests and sequences, coordinating with RTL engineers, and driving formal verification metrics. Candidates should possess a Bachelor's or Master's degree in Computer Engineering or Electrical Engineering. Familiarity with verification tools such as VCS and Cadence is preferred.

Qualifications

• Minimum 8+ years of experience in verification engineering.
• Proven ability to architect and develop complex verification environments.
• Good understanding of computer organization and architecture.

Responsibilities

• Write tests, sequences, and testbench components in SystemVerilog and UVM.
• Coordinate with RTL engineers for logic design and verification.
• Collaborate with multiple engineering teams to develop expertise in design architecture.
• Drive formal verification and write properties to verify the design.
• Responsible for verification quality metrics.

Skills

SystemVerilog

Perl

Ruby

Make

Formal verification tools

RTL design

Computer organization

Education

Bachelor's or Master's in Computer Engineering/Electrical Engineering

Tools

VCS

Cadence

Mentor Graphics

Job description

Themesoft Inc. is seeking an experienced verification engineer based in Austin, TX. The ideal candidate will have over 8 years of experience, particularly in architecting and developing complex verification environments using SystemVerilog. Responsibilities include writing tests and sequences, coordinating with RTL engineers, and driving formal verification metrics. Candidates should possess a Bachelor's or Master's degree in Computer Engineering or Electrical Engineering. Familiarity with verification tools such as VCS and Cadence is preferred.