Senior Verification Engineer - SystemVerilog/UVM, Equity

Broadcom; San Jose (CA); On-site; USD 122,000 - 195,000; Full time

Benefits offered by this job

Medical, dental & vision

401(K) with company matching

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

Paid holidays

Paid vacation

Job summary

Broadcom is seeking qualified individuals to join a high-performance design team working on SoC and IP development. You will contribute to state-of-the-art subsystem verification, collaborating with design and verification teams to meet customer requirements in a fast-paced environment.

The candidate should have extensive SystemVerilog/UVM experience, strong debugging skills, and excellent communication. A Bachelor's degree in EE/CS or equivalent is required, with 8+ years in industry and legal

Qualifications

• Bachelor's degree or equivalent in Electrical and Electronic Engineering, Computer Science, or related field.
• 8+ years of relevant industry work experience.
• Fluent knowledge of RTL verification methodologies including SystemVerilog.
• Strong experience in ASIC design verification flows and DV methodologies.
• Proficient with object-oriented verification languages (OVM, UVM) and scripting (Python, Perl).
• Excellent communication and teamwork skills.

Responsibilities

• Verification environment development using SystemVerilog and UVM.
• Designing verification components such as UVM agents and behavioral models.
• Implementing coverage and assertions using SystemVerilog.
• Developing random and directed test cases against the specification.
• Analyzing and debugging simulation results and coverage.

Skills

SystemVerilog

UVM

RTL verification

C/C++

Perl

Scripting

Education

Bachelor's degree in Electrical and Electronic Engineering, Computer Science, or equivalent

Tools

Emulators

FPGA prototyping

SystemC

C/C++ tooling

Job description

Broadcom is seeking qualified individuals to join a high-performance design team working on SoC and IP development. You will contribute to state-of-the-art subsystem verification, collaborating with design and verification teams to meet customer requirements in a fast-paced environment.

The candidate should have extensive SystemVerilog/UVM experience, strong debugging skills, and excellent communication. A Bachelor's degree in EE/CS or equivalent is required, with 8+ years in industry and legal