RTL Integration Engineer: SystemVerilog & CDC Mastery

Broadcom; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Job summary

Broadcom is seeking a highly capable hardware verification engineer in San Jose to perform IP integration and test/debug at the SoC level. The role includes RTL design, linting, and comprehensive CDC/RDC analysis for RTL and gate-level designs, with synthesis, palladium modeling, and STA support as part of the responsibilities.

The candidate should have deep experience with UVM, SystemVerilog, GLS, and advanced simulation tools (NCSim, VCS), and excel in a fast-paced, globally distributed team.

Qualifications

• Bachelor's degree plus 12+ years related experience.
• Strong understanding of UVM and SystemVerilog.
• Experience with gate-level simulation (GLS).
• CDC analysis for RTL and gate-level designs.
• Familiarity with CDC and SDF simulations; debugging expertise.
• Experience with NCSim and VCS.

Responsibilities

• IP integration and IP test/debug mode verification at the SoC level.
• Create RTL designs, perform linting, and execute CDC/RDC analysis for RTL and gates.
• Handle synthesis, Palladium modeling, and STA support; perform debugging.

Skills

UVM

SystemVerilog

debugging

independent worker

global team

learning new tools

excellent communication

Education

Bachelor's degree

Tools

NCSim

VCS

Job description

Broadcom is seeking a highly capable hardware verification engineer in San Jose to perform IP integration and test/debug at the SoC level. The role includes RTL design, linting, and comprehensive CDC/RDC analysis for RTL and gate-level designs, with synthesis, palladium modeling, and STA support as part of the responsibilities.

The candidate should have deep experience with UVM, SystemVerilog, GLS, and advanced simulation tools (NCSim, VCS), and excel in a fast-paced, globally distributed team.