Senior SystemVerilog DV Engineer – Equity Eligible

Broadcom Inc.; San Jose (CA); On-site; USD 143,800 - 230,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

401(k) with company matching

Employee Stock Purchase Program (ESPP)

Paid holidays and sick leave

Job summary

Broadcom Inc. in San Jose, California, is looking for qualified individuals to join their ASIC Product Division. The role involves developing verification environments, analyzing designs, and debugging in a high-performance team. Ideal candidates will have substantial experience in verification methodologies, particularly using SystemVerilog and UVM.

With an annual salary range of $143,800 - $230,000, Broadcom also offers comprehensive benefits including health plans and a 401(k) with matching contributions. Applications are welcome from individuals regardless of background.

Qualifications

• 12+ years of relevant industry work experience.
• Experience verifying designs at system and block level.
• Strong design debugging capabilities.

Responsibilities

• Develop verification environments using SystemVerilog and UVM.
• Design verification components including UVM agents.
• Analyze and debug simulation failures.

Skills

SystemVerilog

UVM

C/C++

Perl

RTL verification methodologies

Education

Bachelor's Degree in Electrical and Electronic Engineering or Computer Science

Job description

Broadcom Inc. in San Jose, California, is looking for qualified individuals to join their ASIC Product Division. The role involves developing verification environments, analyzing designs, and debugging in a high-performance team. Ideal candidates will have substantial experience in verification methodologies, particularly using SystemVerilog and UVM.

With an annual salary range of $143,800 - $230,000, Broadcom also offers comprehensive benefits including health plans and a 401(k) with matching contributions. Applications are welcome from individuals regardless of background.