ASIC Design Verification Engineer

Broadcom Inc.; Irvine (CA); On-site; USD 91,200 - 152,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

401(K) with company matching

Employee Stock Purchase Program

Paid holidays and sick leave

Job summary

Broadcom Inc. is seeking experienced Design Verification engineers to join their team in Irvine, California. This role focuses on verifying designs related to PCIe and host interface technologies, utilizing System Verilog and UVM methodologies.

The ideal candidate will have significant experience in Design Verification and strong teamwork skills. Broadcom offers a competitive salary range of $91,200 – $152,000 along with various benefits including medical, dental, vision plans, and retirement options.

Qualifications

• Strong background in Design Verification for high-throughput Ethernet or similar technologies.
• Proficiency in System Verilog and UVM.
• Experience with constrained random verification and coverage-driven closure.
• Self-motivated with strong teamwork skills.

Responsibilities

• Design and maintain Verification environments using System Verilog and UVM.
• Apply constrained random verification techniques.
• Collaborate with design engineers on PCIe interfaces.
• Contribute to technical leadership and knowledge sharing.

Skills

Design Verification

System Verilog

UVM

Constrained random verification

Team collaboration

Education

BSEE with 8+ years or MSEE with 6+ years

Tools

Python

Perl

VCS

Incisive

Job description

Overview

Broadcom is seeking experienced Design Verification engineers to work on PCIe and host interface technologies. The role involves verifying new designs that evolve rapidly, using constrained random verification methodologies, System Verilog, and UVM.

Key Responsibilities

• Design, implement, and maintain Verification environments using System Verilog and UVM.
• Apply constrained random verification techniques and drive coverage closure.
• Collaborate with design engineers on PCIe and other host interfaces.
• Contribute to technical leadership and knowledge sharing within the team.

Required Qualifications

• Strong background in Design Verification for high-throughput Ethernet or similar technologies.
• Proficiency in System Verilog (TB structures, classes, SVA, etc.) and UVM.
• Experience with constrained random verification and coverage-driven closure.
• Self-motivated, strong teamwork skills, and ability to work well with others.
• Strong understanding of datapath flows.

Preferred Skills

• Experience with PCIe and third-party BFM.
• Object-oriented programming.
• Experience driving completion via coverage closure.

Tools & Languages

• System Verilog (TB structures – Class, SVA, etc.)
• UVM
• VCS, Incisive, or equivalent simulators
• Scripting: Python, Perl, or similar

Experience

• BSEE with 8+ years in related field, or MSEE with 6+ years.

Compensation & Benefits

Salary range: $91,200 – $152,000 per year, plus discretionary annual bonus and equity awards. Broadcom offers medical, dental, and vision plans; 401(K) with company matching; Employee Stock Purchase Program; Employee Assistance Program; paid holidays; paid sick leave and vacation; and compliance with Paid Family Leave and other leaves.

Equal Employment Opportunity

Broadcom is an equal opportunity employer. We consider applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, disability status, or other protected categories. We also consider qualified applicants with arrest and conviction records consistent with local law.