Senior SoC Verification Engineer - UVM & Timing

Broadcom Inc.; San Jose (CA); On-site; USD 101,000 - 162,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(k) matching

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

Company paid holidays

Paid sick leave

Vacation time

Paid Family Leave

Job summary

Broadcom Inc. in San Jose, CA, is seeking an engineer to drive design from specification through timing closure and hand-off to physical design. You will collaborate with Architecture, Verification, and Physical Design teams to mitigate risks and ensure milestones are met, with strong UVM proficiency expected.

Required BSEE with 5+ years in SoC integration; MSEE or PhD preferred. The role offers a competitive base salary with bonus eligibility and equity potential.

Qualifications

• BSEE required.
• 5+ years industry experience with a focus on SoC integration, UVM testbench setup and design debug.
• MSEE or PhD preferred.

Responsibilities

• Take designs from initial specification through timing closure and physical design hand-off.
• Collaborate cross-functionally with Architecture, Verification and Physical Design teams to mitigate risks and meet milestones.

Skills

UVM

SoC integration

Design debugging

Education

BSEE

MS EE / PhD

Job description

Broadcom Inc. in San Jose, CA, is seeking an engineer to drive design from specification through timing closure and hand-off to physical design. You will collaborate with Architecture, Verification, and Physical Design teams to mitigate risks and ensure milestones are met, with strong UVM proficiency expected.

Required BSEE with 5+ years in SoC integration; MSEE or PhD preferred. The role offers a competitive base salary with bonus eligibility and equity potential.