Senior UVM Design Verification Engineer – SoC

Broadcom; San Jose (CA); On-site; USD 101,000 - 162,000; Full time

Job summary

Broadcom seeks an experienced engineer to drive testbench setup and design verification for complex SoC projects in California. You will own from specification through timing closure and hand-off, collaborating with Architecture, Verification and Physical Design teams to mitigate risks and meet milestones.

Excellent UVM proficiency is required, with 5+ years’ industry experience in SoC integration and design debugging.

Qualifications

• 5+ years of industry experience with a focus on SoC integration, UVM test bench setup and design debug.

Responsibilities

• Operate with a high degree of autonomy, taking designs from initial specification through to timing closure and physical design hand-off
• Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule
• High proficiency in UVM

Skills

UVM

SoC integration

design debug

Education

BSEE required, MSEE/PHD preferred

Job description

Broadcom seeks an experienced engineer to drive testbench setup and design verification for complex SoC projects in California. You will own from specification through timing closure and hand-off, collaborating with Architecture, Verification and Physical Design teams to mitigate risks and meet milestones.

Excellent UVM proficiency is required, with 5+ years’ industry experience in SoC integration and design debugging.