Senior Verification Engineer – FPGA/ASIC (Remote)

Pic-Time Ltd.; Denver (CO); Hybrid; USD 130,000 - 200,000; Full time

Benefits offered by this job

Medical

Dental

Vision

PTO

401(k) match

Parental leave

Job summary

Ramon.Space in Englewood, CO is seeking a Design Verification Engineer to join our VLSI team.

You will plan and implement UVM verification environments, develop tests and testbenches, generate the Verification Test Plan, and collaborate with Architecture, Design, SW and Validation teams. The role requires 7+ years of experience, SystemVerilog/UVM expertise, and FPGA tool proficiency. Hybrid work in the Denver area with a competitive salary.

Qualifications

• 7+ years of relevant design verification experience.
• Proficiency in FPGA/ASIC verification development methodology.
• Proficiency in SystemVerilog and UVM.
• Knowledge and experience with FPGA tools (Vivado/Quartus/VCS).

Responsibilities

• Plan & implement UVM verification environments developing tests, testbenches, UVM components, and regressions/test lists.
• Responsible for generating and executing the Verification Test Plan and Verification Requirement Matrix.
• Interact with Architecture, Design, SW and Validation teams.
• Define new DV methodologies and improve existing ones.
• Work on both ASIC and FPGA Space system projects.

Skills

SystemVerilog

UVM

Verification methodology

Testbench development

Tools

Vivado

Quartus

VCS

Job description

Ramon.Space in Englewood, CO is seeking a Design Verification Engineer to join our VLSI team.

You will plan and implement UVM verification environments, develop tests and testbenches, generate the Verification Test Plan, and collaborate with Architecture, Design, SW and Validation teams. The role requires 7+ years of experience, SystemVerilog/UVM expertise, and FPGA tool proficiency. Hybrid work in the Denver area with a competitive salary.