Verification Engineer

Pic-Time Ltd.; Denver (CO); Hybrid; USD 130,000 - 200,000; Full time

Benefits offered by this job

Medical

Dental

Vision

PTO

401(k) match

Parental leave

Job summary

Ramon.Space in Englewood, CO is seeking a Design Verification Engineer to join our VLSI team.

You will plan and implement UVM verification environments, develop tests and testbenches, generate the Verification Test Plan, and collaborate with Architecture, Design, SW and Validation teams. The role requires 7+ years of experience, SystemVerilog/UVM expertise, and FPGA tool proficiency. Hybrid work in the Denver area with a competitive salary.

Qualifications

• 7+ years of relevant design verification experience.
• Proficiency in FPGA/ASIC verification development methodology.
• Proficiency in SystemVerilog and UVM.
• Knowledge and experience with FPGA tools (Vivado/Quartus/VCS).

Responsibilities

• Plan & implement UVM verification environments developing tests, testbenches, UVM components, and regressions/test lists.
• Responsible for generating and executing the Verification Test Plan and Verification Requirement Matrix.
• Interact with Architecture, Design, SW and Validation teams.
• Define new DV methodologies and improve existing ones.
• Work on both ASIC and FPGA Space system projects.

Skills

SystemVerilog

UVM

Verification methodology

Testbench development

Tools

Vivado

Quartus

VCS

Job description

We are looking for a talented Design Verification Engineer to join our VLSI team.

What you will be doing

• Plan & implement UVM verification environments developing tests, testbenches, UVM components, and regressions/test lists
• Responsible for generating and executing the Verification Test Plan and Verification Requirement Matrix
• Interact with Architecture, Design, SW and Validation teams
• Define new DV methodologies and improve existing ones
• Work on both ASIC and FPGA Space system projects

Requirements

• 7+ years of relevant design verification experience
• Proficiency in FPGA/ASIC Verification development methodology
• Proficiency in System Verilog and UVM
• Knowledge and experience with FPGA tools (Vivado/Quartus/VCS)

Advantages

• Experience validating RF Comms, DSP Algorithms, and High Speed SERDES
• Experience validating designs for Space Applications
• Competitive salary and benefits package.
• Benefits at Ramon.Space include medical, dental, vision, PTO, holidays, FSAs, 401(k) match, short term and long-term disability, and parental leave.
• Flexible hybrid working model with opportunities for remote work. The office is located in the Denver Tech Center.
• Collaborative and innovative work environment. Opportunities for professional growth and development.
• Be part of a pioneering team in the satellite communication industry.

The salary range for this position is $130,000 to $200,000. Ramon.Space will consider relevant work experience, skills, education, and training when putting together an offer for this position.

This role involves access to export-controlled technology. Eligibility for such access is subject to U.S. export control laws, and the company may need to obtain appropriate government authorization before granting access.

Ramon.Space is committed to equal employment opportunities.

We might be closer than you think

188 Inverness Drive West suite 225, Englewood, CO 80112, USA