Senior Verification Architect – VCS Deployment & Tapeout

Synopsys; Sunnyvale (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Synopsys is seeking an experienced verification engineer to lead VCS deployments at customer sites and work with design and verification teams to integrate the tool into existing flows. You will diagnose complex simulation mismatches and performance bottlenecks while collaborating with field engineers and R&D to translate customer needs into product improvements.

The role emphasizes scripting, automation, and hands-on debugging across UNIX/Linux environments and Verdi-based workflows, with a

Qualifications

• Bachelor's in Electronics or Computer Engineering or related field; 5+ years experience or Master's with 3+ years in digital design verification.
• Deep hands-on experience with simulation technologies such as VCS or equivalent; strong knowledge of event-driven simulation internals.
• Proficiency in SystemVerilog, UVM, SVA, and HDL languages (Verilog/VHDL) with ability to read and debug complex testbenches and RTL.
• Proven track record debugging simulation mismatches, performance issues, and verification flow problems in production customer environments.
• Strong scripting skills in Perl, TCL, Shell, and Make to automate workflows and improve engineer productivity.
• Working knowledge of UNIX/Linux environments and version control systems; exposure to Verdi and other verification tools.

Responsibilities

• Lead VCS simulation deployments at customer sites, integrating the tool into existing flows and removing adoption blockers.
• Diagnose complex simulation mismatches, performance bottlenecks, and verification environment issues using VCS, Verdi, and debugging infrastructure.
• Collaborate with field application engineers and R&D to translate customer pain points into actionable product requirements and fixes.
• Drive competitive evaluations and benchmarking engagements to demonstrate VCS capabilities.
• Develop automation scripts in Perl, TCL, Shell, and Make to streamline customer workflows and reduce manual steps.
• Interface with product validation and R&D to propose improvements in simulation accuracy, performance, and usability.

Skills

SystemVerilog

UVM

SVA

Verilog

VHDL

Debugging

Automation scripting

Education

Bachelor's in Electronics or Computer Engineering

Master's in related field

Tools

VCS

Verdi

Job description

Synopsys is seeking an experienced verification engineer to lead VCS deployments at customer sites and work with design and verification teams to integrate the tool into existing flows. You will diagnose complex simulation mismatches and performance bottlenecks while collaborating with field engineers and R&D to translate customer needs into product improvements.

The role emphasizes scripting, automation, and hands-on debugging across UNIX/Linux environments and Verdi-based workflows, with a