Senior SoC Design Verification Lead (UVM)

Hewlett Packard Enterprise; Sunnyvale (CA); On-site; USD 174,000 - 353,000; Full time

Job summary

Hewlett Packard Enterprise seeks a visionary Design Verification Manager to lead our silicon verification team in Sunnyvale, CA. You will architect and execute verification strategies for high-performance SoCs, bridging architectural complexity with flawless tape-outs.

You will manage a high-caliber engineering group, drive cutting-edge methodologies, and ensure zero-bug tape-outs. A strong background in SystemVerilog/UVM, formal methods, and emulation is essential.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Science, Computer Engineering or closely related field.
• 10+ years of pre-silicon ASIC/SoC design verification experience.
• 5+ years of dedicated engineering management experience.
• Proven mastery building scalable UVM-compliant testbenches from scratch.

Responsibilities

• Lead a team of design verification engineers; foster technical excellence and collaboration.
• Allocate resources across multiple parallel chip/block schedules.
• Define global verification strategies; own testbench architecture from specs to sign-off.
• Drive industry-leading verification methodology and automated flows across blocks to full-chip level.
• Collaborate with Architecture, RTL Design, Physical Design, and Post-Silicon teams to ensure timely tape-out milestones.

Skills

SystemVerilog

UVM

Formal verification

ASIC/SoC verification

Emulation & hardware acceleration

Education

Bachelor's degree in Electrical Engineering, Computer Science, Computer Engineering

Master's degree in Electrical Engineering or Computer Science

Tools

Palladium

Zebu

Veloce

PCIe Gen6/7

CXL

HBM3

NVLink

Job description

Hewlett Packard Enterprise seeks a visionary Design Verification Manager to lead our silicon verification team in Sunnyvale, CA. You will architect and execute verification strategies for high-performance SoCs, bridging architectural complexity with flawless tape-outs.

You will manage a high-caliber engineering group, drive cutting-edge methodologies, and ensure zero-bug tape-outs. A strong background in SystemVerilog/UVM, formal methods, and emulation is essential.