Senior Verification Architect – Scalable UVM for IP

Credo; Pittsburgh (Allegheny County); On-site; USD 120,000 - 200,000; Full time

Benefits offered by this job

Discretionary bonus

Equity

Medical benefits

Job summary

Credo is seeking a hands-on Verification Engineer to advance digital design verification for our high‑performance networking IP portfolio. You will architect scalable UVM environments, support testbench development, and partner with design teams to deliver production-ready silicon.

The role requires 7+ years of ASIC/SoC verification experience, strong SystemVerilog/UVM skills, and automation scripting in Python/Perl/Tcl; familiarity with Cadence, Mentor, and Synopsys tools is a plus.

Qualifications

• Bachelor’s or master's degree in electrical and/or computer engineering.
• 7+ years in ASIC/SoC verification methodology and execution.
• Strong SystemVerilog, UVM, constrained-random verification, and assertions.
• Automation/scripting in Python, Perl, Tcl, and shell for regressions and reporting.
• Expertise in RTL/testbench debugging and verification sign-off.
• Experience with AI workloads is a plus.

Responsibilities

• Define end-to-end verification strategy and architect reusable UVM-based testbenches for IP and subsystem verification.
• Translate specs into verification plans, test scenarios, checkers, assertions, and coverage models.
• Develop reusable UVM components including agents, drivers, monitors, scoreboards, and reference models.
• Own regression planning, failure triage, debugging, and sign-off criteria.
• Drive coverage closure and identify gaps to improve verification efficiency.
• Collaborate with design, firmware, emulation, and post-silicon teams for robust verification.
• Review microarchitecture for testability and influence design decisions for observability.
• Develop automation infrastructure to improve regressions and stimulus generation.
• Lead design and verification reviews; mentor engineers on methodology and coding quality.
• Support product and field issues with deep understanding of RTL behavior and environment.
• Ensure compliance with standards and specifications; evaluate AI-driven verification techniques.

Skills

Digital design verification

UVM expertise

Testbench development

Python/Perl/Tcl scripting

Debugging complex systems

Verification leadership

State machines and data paths

Networking knowledge (Ethernet, PCIe,

Education

Bachelor’s or master's degree in electrical and/or computer engineering

Tools

Cadence

Mentor

Synopsys

Job description

Credo is seeking a hands-on Verification Engineer to advance digital design verification for our high‑performance networking IP portfolio. You will architect scalable UVM environments, support testbench development, and partner with design teams to deliver production-ready silicon.

The role requires 7+ years of ASIC/SoC verification experience, strong SystemVerilog/UVM skills, and automation scripting in Python/Perl/Tcl; familiarity with Cadence, Mentor, and Synopsys tools is a plus.