Senior Applications Engineer — VCS & Verification Lead

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 170,000 - 210,000; Full time

Job summary

Synopsys, Inc. seeks an experienced verification professional to lead VCS deployments at customer sites, diagnose complex simulation issues, and translate customer pain points into actionable product requirements.

You will collaborate with field engineers and R&D to validate fixes in real customer environments, drive competitive evaluations, and develop automation to streamline workflows. You will work across time zones with global teams to improve simulation accuracy, performance, and

Qualifications

• Bachelor's or Master’s in Electronics or Computer Engineering with 3+ years for Master’s or 5+ years for Bachelor’s in verification
• Strong hands-on experience with simulation technologies (VCS or equivalent) and event-driven simulation internals
• Proficiency in SystemVerilog, UVM, SVA; HDL languages (Verilog, VHDL) and ability to debug complex testbenches and RTL
• Proven track record debugging simulation mismatches, performance issues, and verification flow problems in production environments
• Strong scripting skills (Perl, TCL, Shell, Make) to automate workflows and build tooling
• Working knowledge of UNIX/Linux, version control, and large-scale verification infrastructure
• Exposure to Verdi, low-power simulation, gate-level verification, and functional safety methodologies is a plus

Responsibilities

• Lead VCS simulation deployments at customer sites, integrating the tool into existing flows and resolving adoption blockers
• Diagnose complex simulation mismatches, performance bottlenecks, and verification environment issues using VCS, Verdi, and related tooling
• Collaborate with field application engineers and R&D to convert customer pain points into product requirements and validate fixes in real customer environments
• Drive competitive evaluations and benchmarking engagements, showcasing VCS capabilities and driving adoption
• Develop automation scripts in Perl, TCL, Shell, and Make to streamline customer workflows and improve throughput
• Coordinate with product validation and R&D to propose improvements in simulation accuracy, performance, and usability
• Support customers using advanced verification methodologies including UVM, SVA, low-power simulation, gate-level verification, and functional safety flows

Skills

SystemVerilog

UVM

SVA

Verilog

VHDL

Education

Bachelor's in Electronics or Computer Engineering

Master's in Electronics or Computer Engineering

Tools

Verdi

VCS

UNIX/Linux

Make

Perl

TCL

Job description

Synopsys, Inc. seeks an experienced verification professional to lead VCS deployments at customer sites, diagnose complex simulation issues, and translate customer pain points into actionable product requirements.

You will collaborate with field engineers and R&D to validate fixes in real customer environments, drive competitive evaluations, and develop automation to streamline workflows. You will work across time zones with global teams to improve simulation accuracy, performance, and