Design Verification Lead - Must be local to TX,CA or MA

MTK Technologies; Austin (TX); Presencial; USD 120.000 - 150.000; Jornada completa

Descripción de la vacante

A leading technology firm in Austin is seeking a Design Verification Lead with 15+ years of experience to ensure the functionality of digital designs. You will develop sophisticated test plans and build verification environments using SystemVerilog and UVM methodologies. The ideal candidate possesses strong analytical skills, a Bachelor's or Master's degree in a related field, and familiarity with HDLs and industry-standard simulators. The role is onsite, emphasizing essential collaboration and communication abilities.

Formación

• 15+ years of hands-on experience in digital design verification.
• Expert-level knowledge of UVM or OVM methodologies.
• Familiarity with standard interfaces like AMBA, PCIe, USB, or Ethernet.

Responsabilidades

• Develop detailed test plans based on architectural specifications to identify failure points.
• Build and maintain verification environments using SystemVerilog and UVM.
• Write directed and constrained-random test cases to cover design scenarios.
• Define and implement coverage models; analyze reports to close coverage holes.

Conocimientos

SystemVerilog proficiency

Analytical thinking

Attention to detail

Cross-functional teamwork

Educación

Bachelor’s or Master’s in Electrical, Electronics, or Computer Engineering

Herramientas

VCS

Questa

Xcelium

Descripción del empleo

Overview

Role: Design Verification Lead (15+ years)

Duration: 12+ Months Contract

Location: Austin, TX / Bay area, CA / Boston, MA | Onsite Role

Job Description: We are looking for a skilled Design Verification Engineer to ensure the robustness and functionality of our next-generation digital designs. You will be responsible for \"breaking\" the design by creating sophisticated test environments, identifying critical bugs before tape-out, and ensuring 100% functional coverage.

Responsibilities

• Verification Planning: Develop detailed test plans based on architectural specifications to identify all likely points of failure.
• Testbench Development: Build and maintain scalable, reusable verification environments from scratch using SystemVerilog and UVM (Universal Verification Methodology).
• Test Case Creation: Write directed and constrained-random test cases to cover corner scenarios and ensure design completeness.
• Coverage Closure: Define and implement functional and code coverage models; analyze reports to identify and close coverage holes.
• Debug & Analysis: Use waveform tools (e.g., Verdi, DVE) to debug simulation failures and collaborate with RTL designers to resolve root causes.
• Formal Verification: (Optional/Senior) Apply formal tools to prove design properties and catch complex bugs that simulation might miss.
• Automation: Develop scripts (Python, Perl, or Shell) to automate regression runs and result parsing.

Required Skills & Qualifications

• Education: Bachelor’s or Master’s degree in Electrical, Electronics, or Computer Engineering.
• Experience: [X]+ years of hands-on experience in digital design verification.
• HDLs: Proficiency in SystemVerilog and basic knowledge of Verilog/VHDL.
• Methodologies: Expert-level knowledge of UVM or OVM.
• Protocols: Familiarity with standard interfaces like AMBA (AXI/AHB/APB), PCIe, USB, or Ethernet.
• Tools: Proficiency with industry-standard simulators such as VCS, Questa, or Xcelium.
• Soft Skills: Strong analytical thinking, attention to detail, and the ability to work in a cross-functional team.

Preferred/Bonus Skills

• Experience with low-power verification (UPF/CPF).
• Knowledge of C/C++ or SystemC for hardware/software co-verification.
• Exposure to emulation platforms like Palladium or Veloce.