Senior ASIC & FPGA Verification Engineer - Remote

Aleron; Scottsdale (AZ); Híbrido; USD 88.000 - 125.000; Jornada completa

Descripción de la vacante

Acara Solutions is seeking an experienced Advanced ASIC/FPGA Verification Engineer to drive verification strategy and build robust UVM environments for mission‑critical digital designs in a defense context.

You will collaborate with design, FPGA, ASIC, and systems teams, develop constrained‑random test scenarios, and perform RTL simulations to ensure functional correctness and coverage closures across the lifecycle.

Formación

• 5+ years ASIC/FPGA verification or hardware verification with B.E./B.S.
• 5+ years SystemVerilog and UVM experience.
• 3+ years UVM testbenches, BFMs, or scoreboards.
• 3+ years RTL simulation in Linux (Questa/ModelSim).
• 3+ years constrained‑random verification, assertions, coverage.
• 2+ years verification planning and coverage analysis.
• 2+ years scripting (Python/Tcl/Shell).
• Bachelor’s in Electrical/Computer Science or related field.

Responsabilidades

• Define and execute ASIC/FPGA verification strategies.
• Develop and maintain UVM environments and testbenches.
• Create test plans, verification methodologies, and documentation.
• Develop constrained‑random scenarios, assertions, scoreboards, coverage.
• Perform RTL simulation and debug failures; validate functionality.
• Support verification traceability and coverage closures.
• Collaborate with design/integration teams on architecture and interfaces.
• Contribute to engineering best practices and process improvements.
• Assist FPGA/ASIC hardware integration and validation.

Conocimientos

SystemVerilog/UVM

RTL verification

Constrained‑random

Python scripting

Debug FPGA/ASIC

Team collaboration

Verilog/VHDL

Educación

Bachelor's degree in EE/CE/CS

Master's degree in related field

Herramientas

Questa

ModelSim

UVM testbenches

QVIP

Descripción del empleo

Acara Solutions is seeking an experienced Advanced ASIC/FPGA Verification Engineer to drive verification strategy and build robust UVM environments for mission‑critical digital designs in a defense context.

You will collaborate with design, FPGA, ASIC, and systems teams, develop constrained‑random test scenarios, and perform RTL simulations to ensure functional correctness and coverage closures across the lifecycle.