Lead Digital Verification Engineer – ASIC & SystemVerilog

European Tech Recruit; City of Rochester (NY); Sur place; USD 180 000 - 260 000; Plein temps

Résumé du poste

European Tech Recruit is seeking a Principal Digital Verification Engineer to spearhead digital verification strategies for ASIC and optical networking products. The role involves collaboration with systems engineers and architects to define verification plans, and leadership of verification initiatives across the project lifecycle.

The ideal candidate brings 12+ years of SystemVerilog/UVM/SVA experience, DSP know-how, and a track record of mentoring teams.

Qualifications

• Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, Computer Science or another applicable scientific discipline.
• 12+ years of experience using SystemVerilog, UVM, SVA and major-vendor simulators in digital verification environments.
• Experience with Digital Signal Processing (DSP).
• Experience using Jira for bug tracking.

Responsabilités

• Analyse project architectures and functional requirements in collaboration with systems engineers and architects.
• Validate digital subsystems using simulation, formal verification and coverage methodologies.
• Create, review and optimise simulation environments, test scenarios, functional coverage plans and formal verification test plans.
• Lead focused technical initiatives and mentor team members where required.
• Estimate project schedules, track progress against approved plans and communicate status updates.
• Lead verification activities as an ASIC Verification Prime when assigned.
• Participate in architectural and design reviews to identify verification impacts and opportunities to improve coverage and schedule execution.

Connaissances

Digital verification

SystemVerilog

UVM

SVA

DSP

Formation

Bachelor’s degree or higher in Electrical Engineering, Computer Engineering or Computer Science

Outils

Jira

Description du poste

European Tech Recruit is seeking a Principal Digital Verification Engineer to spearhead digital verification strategies for ASIC and optical networking products. The role involves collaboration with systems engineers and architects to define verification plans, and leadership of verification initiatives across the project lifecycle.

The ideal candidate brings 12+ years of SystemVerilog/UVM/SVA experience, DSP know-how, and a track record of mentoring teams.